VLSI Architecture for Real Time Image Processing
Indian Institute of Technology, Roorkee
Image processing is widely used in fields such as entertainment, healthcare, defence, etc. Some of these image processing applications are bounded by real time constraints. Hardware implementation of real-time image processing (IP) algorithms requires highly efficient VLSI architectures that should dissipate low power without compromising the performance. Various real-time embedded platform such as General Purpose Processors (GPPs), Field Programmable Gate Arrays (FPGAs), Digital Signal Processors (DSPs) and Application Specific Integrated Circuits (ASICs) are used to implement the IP techniques having low to moderate computational complexity. Multi core general-purpose processors architecture with limited memory are used for computer graphic applications. However, due to ever increasing requirement of high definition multimedia, much more memory space and computational resources are needed to achieve better performance. Hybrid architecture based on FPGA and DSP are more suitable for real-time IP techniques having complex computational requirement. In such systems, FPGA provides parallel processing and supports most of the I/O standard whereas, DSP suffices the floating point computation and high speed in-built multiplier and accumulator requirements. This talk will deal with state-of-the art VLSI architectures for implementation of real time image processing algorithms.